As high-resolution technology in liquid crystal display devices advances, the period for sampling data to be supplied to data signal lines by dot sequential driving is becoming increasingly short. Data is supplied to the data signal lines in accordance with switching on/off of analog switches, whose operation is controlled by sampling pulses that determine the period for sampling data. Thus, constantly carrying out normal display requires ending the sampling by sampling pulses within a data supply period for each data signal line. Specifically, continuing sampling beyond the data supply period into a period for supplying next data causes the potential of data signal lines to be disturbed due to different data. This indicates that preventing delay in such sampling pulses is important. In addition, even when a sampling pulse in a specific data signal line ends within its data supply period, rising of a sampling pulse in an adjacent data signal line before the above sampling pulse ends causes the potential charged in the specific data signal line by the time of the rising to be leaked into the adjacent data signal line, thereby disturbing the potential. This indicates that it is also important to secure an interval between adjacent sampling pulses so that they do not overlap each other.
Liquid crystal display devices with high resolution have extremely short data supply periods. This makes it highly difficult to keep the delay in sampling pulses within the data supply period and also to secure the interval between such sampling pulses.
Patent Literature 1 discloses an arrangement that simultaneously suppresses the delay and sufficiently secures the interval between sampling pulses.
FIG. 10 is a view illustrating an arrangement of a source driver 103 in a liquid crystal display device disclosed in Patent Literature 1.
The source driver 103 has latch stages, namely the i-th latch stage, the (i+1)th latch stage, the (i+2)th latch stage, . . . , which together constitute a shift register. Each of the latch stages includes a level shifter LS and an asynchronous set-reset flip-flop SR_FF. The level shifter LS level-shifts a clock signal SCK or SCKB so that internal circuits of the source driver 103 are driven. The level shifter LS supplies outputs OUTB to an inverted set input terminal SB of the set-reset flip-flop SR_FF. The clock signal SCK has a waveform illustrated in FIG. 11. The clock signal SCKB is an inverted signal of the clock signal SCK. When fed with active enable signals, level shifters LS in the odd latch stages level-shift one of the clock signals SCK and SCKB, while those in the even latch stages level-shift the other.
The set-reset flip-flop SR_FF supplies outputs Q to an enable terminal ENA of a level shifter LS in the next latch stage, as well as to a delay inverter circuit 103a as outputs to be fed into a sampling circuit block 101a. The set-reset flip-flop SR_FF has a reset terminal that is fed with outputs Q from a set-reset flip-flop SR_FF in the next latch stage. The delay inverter circuit 103a supplies outputs to a level shifter 103b. The level shifter 103b supplies sampling pulses from its output OUTB in response to enable signals, i.e., the outputs Q from the set-reset flip-flop SR_FF in the next latch stage. Sampling pulses outputted are supplied sequentially into analog switches ASW (Ri), ASW (Gi), ASW (Bi), ASW (Ri+1), . . . of the sampling circuit block 101a, where sampling is performed on data DATA(i), DATA(i+1), . . . (each including distinct portions for R, G, and B) that are supplied within their respective data supply periods.
FIG. 11 is a signal timing chart of the above operation. The output Q(i) represents an output Q from the i-th set-reset flip-flop SR_FF. The output Q(i) is generated after a clock signal SCK is level-shifted by a level shifter LS and is then fed into the set input terminal SB. The output Q(i) is a signal that starts when a delay time Ta, i.e., the sum of (i) an internal delay time of the level shifter LS and (ii) an internal delay time of the set-reset flip-flop SR_FF, has elapsed after the clock signal SCK rises. The output Q(i) is reset by an output Q(i+1) from a set-reset flip-flop SR_FF in the next latch stage. Thus, the output Q(i) ends when the internal delay time Tb of the set-reset flip-flop SR_FF has elapsed after the timing at which the output Q(i+1) starts. The output Q(i+1) is a signal that starts when the delay time Ta has elapsed after the clock signal SCKB rises. The output Q(i) is delayed by a delay inverter circuit 103a so as to change into an input signal to be fed into an input terminal IN of a level shifter 103b. 
The level shifter 103b supplies an output OUTB that starts at the timing at which the input signal into the input terminal IN starts. In contrast, since the set-reset flip-flop SR_FF in the next latch stage supplies the output Q(i+1) to an enable terminal EN of the level shifter 103b, the output OUTB ends at timing earlier than the timing at which the input signal into the input terminal IN ends, i.e., at timing defined by the timing at which the input signal into the enable terminal EN ends. As illustrated in FIG. 11, this consequently allows for generation of a sampling pulse having a delay with a portion trimmed, the portion being represented by the area filled with diagonal lines and corresponding to the sum of (i) the delay time Tb and (ii) a delay time due to the delay inverter circuit 103a. Further, as illustrated in FIG. 11, this delay trimming allows for a sufficient interval between the sampling pulse and another sampling pulse generated in the next latch stage.